Electric timer with nonvolatile memory

ABSTRACT

Disclosed is an electronic digital timer with a nonvolatile memory particularly adapted for use in the fuze of an artillery projectile. The timer comprises a main counter in the form of a series of integrated circuit flip-flops, each having its own memory. A predetermined count is set into the memories in the form of MNOS transistors and complemented in the counter when power is restored. A fuze oscillator actuates the counter through a frequency divider and scaler. A setter is used to set and monitor the timer.

O United States Patent [151 3,654,496

Flad [451 Apr. 4, 1972 541 ELECTRIC TIMER WITH 3,418,646 12/1968 Marcus ..307/238 x NONVOLATILE MEMORY 3,454,785 7/1969 Norman et al.. ..307/221 3,067,684 12/1962 Euker et a1 ....102/70.2 R 1 lnvemofl Fl'kdrkh Flld, Rockvlller 3,500,746 3/1970 Ambrosini ..102/70.2 R

[73] Assignee: The United States oi America as represented by the Secretary oi the Army b I El OTHER PUBLICIATIONS I Pu ectronics Review" in E ectronics Vo 41, No. 22, [221 Dated Oct. 28, 1968 p. 49- so. [21] Appl. No.: 33,458

Primary Examiner-Donald D. Forrer Related 1.1.8. Application Data Assistant Examiner--R. E. Hart lcgtsinuation-in-part of Ser. NO. 845,001, July 25. saragov'tz'fidward J'KellyHerbe'me [57] ABSTRACT [52] U.S.Cl. ..307/304,307/221 5 [MCL I I 03 19 03 Disclosed is an electronic digital timer with a nonvolatile [58 1 Field 01 Search ..307/221-22s, 23s, memory Pwiwlarly adapted for use in the fun of an artillery 307/279, 323/37, 43, 484, 7245, 1 19, 129 projectile. The timer comprises a main counter in the form of 102/702 R a series of integrated circuit flip-flops, each having its own memory. A predetermined count is set into the memories in [56] Rehrences cited the form of MNOS transistors and complemented in the counter when power is restored. A fuze oscillator actuates the UNITED STATES PATENTS counter through a frequency divider and scaler. A setter is used to set and monitor the timer. 3,137,818 6/1964 Clapper ..328/37 X 3,191,061 6/ 1965 Weimer ..307/221 12 Claims, 6 Drawing Figures Rial IEFRZ /22 26 IN 61:] I 4 '2 o l1 i an M MEMORY Q3 P X RESET/SET (N a Q13 Q17 1 L 04 14 mi 102 Q1 m2 05 F GROUND 28 11 SHORT PULSE LP 34 LONG PULSE PATENTEUAFR M972 3,654,496

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SHEEN; 0F 4 MEMORY CIRCUITS A0 A1 l8 T MEMORY I l I RESET/SET I BIAS ,CKT. 72 VDD LI 1 R Q6 GROUND 24 READOUT INTEGRATED CIRCUIT MEMORY I RESET/SET I FLIP FLOP I 76 A l GROUND I v SHORT PULSE RESET 54 CIRCUIT CLOCK LONG PULSE I INVENTOR FRIEDRICH w. FLAD Hm? I o I BY W M 7 ATTORNEYS ELECTRIC TIMER WITH NONVOLATILE MEMORY This application is a continuation-in-part of copending application Ser. No. 845,001 filed 25 July 1969.

This invention relates to an integrated circuit timer and more particularly to a simplified and inexpensive timer construction having increased reliability of operation. The timer can be set and reset an unlimited number of times and, after setting, it remembers the time setting without power being applied. During setting, the oscillator of the timer is calibrated and all circuits are checked for proper operation.

The timer of the present invention is constructed for usein time fuzes of artillery rounds. The fuze power supply is spin and setback activated. This means that no power is available to the timer prior to firing. For the setting operation, power is supplied by a setting box. After setting, the fuze is disconnected from the setting box. This requires that the timer memory maintain its information without the application of power. To meet this requirement, the timer of the present invention employs memory elements in the form of P-channel insulated gate field effect transistors with silicon nitride as gate insulator and a thin silicon dioxide layer between the silicon surface and the nitride layer, hereafter referred to as MNOS transistors. These devices are capable of storage without power and are compatible with the printed circuitry and integrated circuit techniques used in manufacturing the more conventional MOS transistors.

Various timers have been proposed in the past but none has been found suited for use in time fuzes of artillary rounds. Timers utilizing magnetic core counters have the capability of memory without power but because of their large size and bulk and their high cost of manufacture, they are not suited to fuze applications. Timers with fusible links as memory elements can be produced by integrated circuit techniques but have only a limited number of resets because the burning out of the fuze links is not reversible. Finally, timers with ferroelectric memories need polarization voltages of about 200 volts or more and thus require complicated and expensive interface equipment between memory elements and the counter.

In order to avoid these and other difficulties, there is disclosed in copending application Ser. No. 845,001 filed 25 July 1969 an improved electronic timer in the form of a small, lightweight, and inexpensive fuze timer which can be manufactured using more or less conventional integrated circuit techniques. The timer of that application comprises integrated MOS counters supplemented by an integrated programmable decoder consisting of MNOS transistors. Charge storage in the dielectric of the MNOS transistors is used to achieve memory without power.

The timer of the present invention is of the same general type but is of simplified, less expensive, and more reliable construction. In the present invention, the memory devices are MNOS transistors and are combined with flip-flops to form a series of count stages comprising a main counter. This counter is energized through novel reset logic circuit and integrated circuit scaler to form an improved fuze timer which achieves high reliability and accuracy in an economical way. The integrated portion of the timer may be formed from approximately 600 transistors.

It is therefore one object of the present invention to provide an improved electronic timer with a nonvolatile memory.

Another object of the present invention is to provide an improved remote resettable electronic timer.

Another object of the present invention is to provide an electronic timer utilizing MNOS transistors.

Another object of the present invention is to provide a fuze timer of simplified and less expensive construction and yet one which evidences the improved reliability and accuracy of operation.

Another object of the present invention is to provide a spin and setback activated timer particularly adapted for use in the time fuzes of artillary rounds.

Another object of the present invention is to provide a timing system which automatically adjusts the setting of the system for deviations of the oscillator frequency from its nominal value.

7 Another object of the present invention is to provide an improved reset circuit for fuze timers.

Another object of the present invention is to providean improved memory arrangement particularly adapted for fuze constructions.

Another object of the present invention is to provide an improved fiip-flop circuit with a nonvolatile memory.

Another object of the present invention is to provide a preset counter with a nonvolatile memory.

These and further objects and advantages of the invention will be more apparent upon reference to the following specification, claims, and appended drawings, wherein:

FIG. 1 is a simplified circuit diagram of a memory circuit incorporating an MNOS transistor;

FIG. 2 is a circuit diagram of a binary stage incorporating a nonvolatile memory of the type illustrated in FIG. 1;

FIG. 3 is a block diagram and logic circuit for a complete fuze timer;

FIG. 4 is a more detailed circuit diagram of the reset circuit forming part of the timer of FIG. 3;

FIG. 5 is a more general showing of an MNOS memory arrangement; and

FIG. 6 is a general showing of a flip-flop circuit with a nonvolatile memory.

The'digital timer of the present invention comprises a time base and an accumulator. In the preferred embodiment, the accumulator takes the form of a digital counter. This counter is advanced one count after each period of the time base. If at time T 0, the state of the counter was 0, the state of the counter at time T, represents the lapsed time between T and T, in units of time base periods. At time T,, the timer produces an output signal which initiates a function such as activating a fuze firing circuit. Alternatively, the timer may produce an output signal when the counter reaches its maximum corresponding to T In order to obtain the output signal at T, and not at T the counter must start at T 0 from a state corresponding to the time complement T T,.

The time delay T, is variable and is programmed electrically .by a setting box, requiring not more than three connections between the setting box and timer. The maximum number of connections eliminates the possibility of providing for parallel setting or parallel resetting of the counter. For this reason, the sealer is bypassed during counter setting so that the counter may be set at a more rapid rate. The counter incorporates its own memory or decoder and stores the information corresponding to T,. During the timing operation, the counter counts up to T and when this count is achieved, an output signal is generated.

The timer of the present invention utilizes metal nitride oxide silicon transistors which are P-channel insulated gate field effect devices. A polarizing voltage of sufficient amplitude applied across the dielectric changes the threshold voltage by an amount that depends on the amplitude and duration of the polarizing voltage and has the same polarity as the polarizing voltage that causes it. The change in threshold voltage is permanent and can be reversed only by applying a polarizing signal of opposite polarity. If the gate voltage has to exceed the supply voltage to change the threshold voltage, these devices can be used in logic circuits and as memories.

Referring to FIG. 1, that FIGURE shows a memory circuit generally indicated at 10 and comprising a memory transistor or MNOS 12, labeled Q1, an MOS transistor 14, labeled Q2, and a l megohm bias resistor 16. In FIG. 1 and in the subsequent FIGURES of the drawings, the memory transistors are circled, whereas the transistors which do not act as memories are uncircled. The gate of transistor 12 is connected by lead 18 to a memory reset/set source and through resistor 16 by way of lead 20 to a bias source. The drain of transistor 12 is connected by lead 22 to a drain voltage source V,,. The gate of transistor 14 is coupled to a readout signal source by way of lead 24.

In the circuit shown in FIG. 1, transistor 12, labeled Q1, is used as a memory and transistor 14, labeled Q2, as a switch. A positive polarizing voltage applied to the memory reset/set line 18 shifts the threshold voltage of Q1 positive to V (reset state). This is not affected by the voltage V,, or the state of transistor 14', which is normally not conducting. A negative polarizing voltage produces a conducting channel in the substrate of Q1. Therefore, the drain, the inverter substrate surface, and the source of Q1 are practically at the same potential, namely, at V Hence, the voltage across the dielectric is equal to the difference between the polarizing voltage and V The threshold voltage of O1 is shifted negatively to V (set state) if V 0, and remains unchanged if V,, is sufficiently negative. The bias voltage is selected so that Q1 is conducting in the reset. state (V =V and not conducting in the set state (V, V During a negative readout pulse, 01 and Q2 form a low impedance path if Q1 is in the reset state, and a high impedance path if 01 is in the set state.

FIG. 2 shows the memory circuit of FIG. 1 used to set a flipflop, generally indicated at 26 in FIG. 2, to its initial state. In FIG. 2, like parts bear like reference numerals and the memory transistor Q3 is the transistor 12 of FIG. 1 and transistor O4 is the switching transistor or MOS device 14. Output M corresponds to V,, in FIG. 1. A positive reset signal puts Q3 always into the conducting state. Whetheror not Q3 is switched to the nonconducting state by a negative pulse depends on the voltage at node M. When power is turned on, a short and a long reset pulse are generated on leads 28 and 30, respectively, as indicated at 32 and 34. This makes the flipflop 26 always come up in the I state (M low) after a memory reset signal. If power is turned off, and turned on again after a negative set pulse, the initial state of the flip-flop is the complement of its state at the time of the negative memory set signal.

FIG. 3 is a logic diagram of a complete timer generally indicated at 30. The timer comprises a fuze oscillator 32, preferablyoperating at l0.24 kHz. and a fuze power source 34. Oscillator 32 is connected through a frequency divider, generally indicated at 36, and an isolation circuit 38 to a scaler 40. The output of scaler 40 is applied to the input of a main counter 42 having its stages connected in parallel through gate 44 to transistors 46 and 48 which act to complete an arming circuit by way of lead 50 and a firing circuit by way of lead 52.

Main counter 42 is connected to a reset logic circuit, generally indicated at 54, to an integrated feedback logic circuit 56 and receives a memory reset/set signal by way of lead 58. A setter, generally indicated at 60, is adapted to be connected to the timer 30 by three connections, namely, a ground connection 62, an external power connection 64, and a monitor line connection 66. The setter 60 is coupled to the various components of the timer by way of a signal separation circuit 68 including discrete components. The remainder of the timer, i.e., that portion of the timer with the exception of the oscillator 32, fuze power supply 34, and discrete components enclosed by the dashed box 70, are all preferably formed of integrated circuit components.

The frequency of fuze oscillator 32 is first divided by 2 in the frequency divider 36 and then is divided by 512 in the scaler 40, which scaler is in the form of a binary counter without a memory. The action of the scaler 40 is similar to that shown and described in my copending application Ser. No. 845,001, filed 25 July 1969 the disclosure of which is incorporated herein by reference. The output frequency of the scaler at S8 is Hz, and represents the input signal for the main counter 42 in a timing operation. To set the timer at an accelerated rate, the scaler and main counter are both operated from the 5.12 kI-lz. clock signals available at gate G4.

The operation of the timer is based primarily on the main counter 42 which comprises a plurality of bistable or flip-flop counting stages each incorporating its own memory. Before the power is turned on, all of the memories in the counter 42 are reset by a reset signal. This makes all of the flip-flops in the counter come up in the l state; the setter turns on the control gate in the correct phase relationship with the oscillator. The turn off of the control gate is controlled by a time selector and a precision oscillator in the setter. The gate time is controlled by the precision oscillator, therefore the number of counts in the counter at the time the gate is shut off is adjusted for a deviation of the oscillator 32 from its standard frequency.

Once the count is completed, the memories are set by the application of a set signal from the setter. Power is then turned off. Whenever power is turned on, such as by the activation of the fuze power supply 34 due to setback and spin of an artillery shell in which the fuze is incorporated, the initial state of the counter 42 is the complement of the set time. If an output signal to-the firing circuit by way of lead 52 is generated when the main counte'r changes from the all "I" state to the all 0" state, this output signal occurs delayed by the desired time after fuze power has been turned on to the timer.

The reset logic circuit 54 generates a pair of reset pulses when power is turned on. This resets the scaler to the all 0" state.

The memory circuit in M9 is connected to M9 instead of M9 (see FIG. 2) and makes M9 come up in the 0" state after a memory reset signal. Complementing, however, is not affected. In M11, the memory Q3 and the switch Q4 are interchanged. This makes M11 come up in the 1" state after a memory reset, and in the 0" state after a memory set. Only three connecting wires to the setter are required, namely, external power, ground, and the monitor line 66 which is shared by the memory reset/set signal, the count control signal, and feedback pulses.

The signal separation circuit 68 splits off the high voltage memory reset/set signal. In the isolation circuit, the monitor line is sampled to determine the position of the count control switch in the setter. The feedback logic circuit 56 generates a composite signal that contains sufficient information about the operational status of the timer to make a go/no-go decision.

The timing operation is as follows. All memories are reset. Then, external power is applied. The scaler comes up in the all 0 state, and all flip-flops in the main counter 42 except M9 are in the l state. The count control prevents the sealer and main counter from counting. The feedback signal provides the phase information for the setter to activate the count control at the beginning of a clock period. With the next sampling pulse, the count control flip-flop G24/G25 switches, and the sealer and main counter count simultaneously. The negative going feedback pulses are counted in the setter. Their duration give information about the state of S8, M11, and G19. The setter checks if changes in these signals occur at the correct count. After 5 I 2 pulses, the main counter is in the all 1" state. The setter starts now counting pulses from a precision oscillator until it reaches a count equivalent to the desired time setting. Then the count control stops the scaler and the main counter, and a negative pulse sets the memories. Since the gate time was controlled by the precision oscillator, the number of counts in the main counter is adjusted frodeviations of the fuze oscillator from its nominal frequency.

To verify the time setting, the sealer and main counter are reset, and the time is measured until the first feedback pulse occurs, which corresponds to the firing signal. If this time is within a given tolerance, the setting operation is complete.

In the timing operation, when the fuze power comes on, the scaler is reset, and the main counter is complemented. Gates G24 and G17 block clock pulses from the main counter input, which is connected to the scaler output through gate G15. Approximately 1 second before M11 changes state, gate G19 generates an arming pulse. When M11 switches, a firing signal is transmitted to the firing circuit by way of lead 52.

Due to the extensive checking carried out in each setting operation, the electronic timer is able to achieve high reliability and accuracy in an economical way since the precision oscillator is part of the ground equipment. The integrated portion of the timer contains approximately 600 transistors. A two chip approach may be taken with the main counter, G18, G19, and bias circuit Q6 and 07 located on the first chip and the sealer with the rest of the circuits on the second chip. Alternatively, all the circuits may be integrated on one chip.

FIG. 4 shows the reset circuit 54 of FIG, 3 in more detail. it is an integrated circuit consisting of either MOS or MNOS transistors. When the supply voltage -V,, is turned on, negative going signals, designated short pulse" and "long pulse," are generated on leads 2B and 30. The clock output is clamped to ground. If V exceeds a level of V,,,,,, which is established by the geometry of Q2 and Q3 in FIG. 4, and the amplitude of the clock pulses from the frequency divider is greater than one threshold voltage, the short pulse on lead 28 is terminated. Half a clock period later, the long pulse disappears. At the same time, gate G4 puts out negative going clock pulses. If the supply voltage should drop below V negative going reset signals are generated and the clock signal ceases. When V exceeds V again, the reset signals are terminated and the clock signal appears again.

FIG. 5 is a more general showing of the memory arrangement illustrated in FIG. 1 and like parts bear like reference numerals. The memory arrangement, generally indicated at '70 in FIG, 5, consists of a bias circuit 72 including transistors 06 and Q7 integrated on one chip with one or more memory circuits 01,02. with additional circuits indicated by the same numbers primed, All transistors in FIG. 5 are MNOS. The gates of all memory transistors 01 are connected to a common reset/set bus 18 and the gates of all the switching transistors 02 are connected to a common readout bus 24. The readout line is normally at ground potential which means that normally none of the transistors 02 are conducting.

The geometry of Q6 and O7 is such that the output voltage at the drain of O7 is slightly more than the threshold voltage of O7 in the unpolarized state. A positive memory reset pulse shifts the threshold voltage of the memory transistors to a more positive value than the bias voltage. This means that all memory transistors 01 are conducting. A negative memory set pulse, that occurs when all memory transistors are in the reset state, shifts the threshold voltage of a memory transistor more negative than the bias voltage if the potential at its corresponding A input is close to ground and the threshold voltage remains unchanged, if the potential of the A input is sufficiently negative.

For readout, a negative going signal is applied to the readout line. This turns on all transistors 02. There is a low impedance from A to ground during readout if the corresponding memory transistor is conducting and a high impedance if the memory transistor is not conducting. The readout is nondestructive and it requires no power to maintain the information stored in the memories.

An advantage of the memory is that the high voltage memory reset/set signals appear only on the common gate line of the memories, where they are isolated by a dielectric from the rest of the circuits. No transistors with a breakdown voltage higher than 30 volts are required since write operation can be controlled by A inputs at signal levels which are customary for MOS circuits. Since all transistors are integrated on one chip, bias voltage is automatically adjusted for variations in the threshold voltage of the unpolarized memories from chip to chip or wafer to wafer.

FIG. 6 is a more general showing of the flip-flop or bistable 26 of FIG. 2 with a nonvolatile memory. Like parts in FIG. 6 again bear like reference numerals. This circuit combines one reset circuit, a memory arrangement, and one or more flipflops. The flip-flop is designed in such a way that it can be reset or set by clamping the proper output to ground. It can consist of MOS or MNOS transistors and it can be integrated with the memory or on a separate chip.

The short pulse on lead 28 is connected to the gate of a switching transistor 76 whose drain connects to one output of the flip-flop. The long pulse on lead 30 feeds into the gate of the switching transistor 14 in the memory circuit. The A input of the memory circuit connects to the other side of the flipflop.

'Before the supply voltage V,,,, is turned on, all memories are reset. Then power is turned on. All flip-flops come up in such a state that the output connected to the memory is at ground. At the termination of the long pulse, a clock signal is available at the reset circuit. The flip-flop can be used to perform logic functions that are controlled by additional circuitry.

When a certain state of the flip-flop is to be stored in the memories, a negative memory set signal is transmitted. Whenever the supply voltage drops below its minimum value determined by design of the reset circuit, each flip-flop is reset to the opposite of its state at the time of the negative memory set pulse. After termination of the reset signals, both flip-flop outputs are disconnected from ground and the flip-flop can perform logic functions independent of the state of the memory.

The flip-flop circuits illustrated in FIG. 6 are connected to form a binary counter, such as the main counter 42 of FIG. 3. Before power is turned on, all the memories are reset. This makes all flip-flops come up in "I" state when power is turned on. Now the desired number of pulses n is counted into the counter. A negative memory set signal stores this number in the memories in nonvolatile form. Power can be turned off. When power is turned on again, the initial state of each flipflop is the opposite of its state at the time of the negative memory set pulse. Therefore, the number in the counter is the complement of the number n that has been counted into the counter before the memories were set. This means that after counting n pulses, the counter will be in the all 0" state.

This is not restricted to a binary counter. In a decimal counter, a code can be used in each decade that satisfies the relation: a a 9, where a is an arbitrary number 0 a 9, and a is the number that results if each flip-flop in the decade is complemented. For example, the following code may be used:

The memory circuits must be connected to their corresponding flip-flops in such a way that each decade is reset to 9 if all memories are in the conductive state.

When the main counter, the sealer and the oscillator are combined to form a timer, it is preferable to include a gate circuit to bypass the scaler to feed oscillator pulses into the main counter through a gate controlled by a remote setter so as to increase the setting speed. The memories are reset. Then power is turned on to the timer. This resets the main counter to the all l state. The setter turns on the count control gate in the correct phase relationship with the oscillator. The turn off of the count control gate is controlled by a time selector and a precision oscillator in the setter. The gate time is controlled by the precision oscillator, therefore, the number of counts in the counter at the time the gate is shut off is adjusted for a deviation of the oscillator from its standard frequency.

After the count has been stopped, the memories are set. Power is turned off. Whenever power is turned on, the initial state of the counter will be the complement of the set time. If an output signal is generated when the main counter changes from the all l state to the all 0" state, this output signal occurs delayed by the desired time after fuze power has been turned on to the timer. When power is supplied externally by the setter, the output signal occurs t seconds after the count control gate has been turned on. The delayed time t equals the desired or set time divided by 2, where N is the number of scaler stages. This allows a quick check of the time setting as a part of each setting procedure.

lt is apparent from the above that the present invention provides an improved timer particularly adapted for use in the fuzes of artillery shell and also improved timer components and circuits of simplified and inexpensive construction, and ones which readily adapt themselves to fabrication utilizing conventional integrated circuit techniques. Because of a unique construction and procedure, the timer may be frequently checked and rechecked to increase its reliability and accuracy of operation during the setting process.

Important features of the present invention include a main counter in the form of a flip-flop or counting chain in which the flip-flops are combined with their own memory devices in the form of MNOS transistors. These transistors act as memories which retain their state when power is removed. A predetermined count is inserted or set into the counter and this count is retained after the setting process. When power is restored, such as by firing of the projectile, the original count set into the main counter is complemented, i.e., the counter assumes the complementary state to the preset count. Timing then occurs by the means of pulses from a fuze oscillator until a predetermined state is reached such that all the stages of the main counter arrive at the same state. For example, if the main counter is initially reset so that all stages are in the l state, firing occurs after complementing when a number of pulses has been counted sufficient to return the counter so that all stages are in a state.

For rapid setting, the scaler is preferably bypassed, i.e., the oscillator is connected directly to the main counter as well as the scaler. Setting is achieved from the fuze oscillator by permitting the fuze oscillator to set the counter over a predetermined length of time as determined by a precision oscillator in the setter. Such an arrangement automatically compensates for variations in the fuze oscillator frequency.

The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

What is claimed and desired to be secured by United States Letters Patent is:

l. A digital timer comprising a main counter including a plurality of counting stages, means coupled to said counter for inserting a predetermined count into said counter, means in said counter for complementing said predetermined count in said counter, and means responsive to a predetermined condition of said counter for producing an electrical output signal from said timer.

2. A timer according to claim 1 wherein said stages are binary stages.

3. A timer according to claim 2 wherein each stage of said counter includes a solid state memory device.

4. A timer according to claim 3 wherein said counter is made of integrated circuit components.

5. A timer according to claim 4 wherein said solid state memory devices comprise MNOS transistors.

6. A timer according to claim 5 wherein said stages include flip-flops formed by insulated gate field efiect transistors.

7. A timer according to claim 6 wherein each said stage includes an MNOS memory and an insulated gate field effect transistor switch, the source-drain circuits of said memory and switch being connected in series.

8. A timer according to claim 1 including a fuze oscillator, and a scaler coupling the output of said fuze oscillator to the input of said main counter.

9. A timer according to claim 8 including gate means for coupling the output of said oscillator directly to said main counter during settin of said timer.

10. A timer accor mg to claim 1 including a reset logic circuit coupled to said counter for automatically resetting said counter in response to variations in timer voltages.

11. Apparatus according to claim 1 including a setter coupled to said timer, and a feedback logic circuit coupling the output of said timer to said setter.

12. Apparatus according to claim 11 including a ground line, an external power line, and a monitor line coupling said setter to said timer. 

1. A digital timer comprising a main counter including a plurality of counting stages, means coupled to said counter for inserting a predetermined count into said counter, means in said counter for complementing said predetermined count in said counter, and means responsive to a predetermined condition of said counter for producing an electrical output signal from said timer.
 2. A timer according to claim 1 wherein said stages are binary stages.
 3. A timer according to claim 2 wherein each stage of said counter includes a solid state memory device.
 4. A timer according to claim 3 wherein said counter is made of integrated circuit components.
 5. A timer according to claim 4 wherein said solid state memory devices comprise MNOS transistors.
 6. A timer according to claim 5 wherein said stages include flip-flops formed by insulated gate field effect transistors.
 7. A timer according to claim 6 wherein each said stage includes an MNOS memory and an insulated gate field effect transistor switch, the source-drain circuits of said memory and switch being connected in series.
 8. A timer according to claim 1 including a fuze oscillator, and a scaler coupling the output of said fuze oscillator to the input of said main counter.
 9. A timer according to claim 8 including gate means for coupling the output of said oscillator directly to said main counter during setting of said timer.
 10. A timer according to claim 1 including a reset logic circuit coupled to said counter for automatically resetting said countEr in response to variations in timer voltages.
 11. Apparatus according to claim 1 including a setter coupled to said timer, and a feedback logic circuit coupling the output of said timer to said setter.
 12. Apparatus according to claim 11 including a ground line, an external power line, and a monitor line coupling said setter to said timer. 